Understanding the Criticality of Stencil Aperture Design and Implementation for a QFN Package

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1 Power Matters Understanding the Criticality of Stencil Aperture Design and Implementation for a QFN Package Larry Bright & Greg Caswell November 2013

2 Agenda Overview Problem Description Analysis Stencil Design Addressing Manufacturing Yields Improving Reliability PCB and Stencil Recommendations Discussion Conclusion 2

3 Overview 164 pin Dual Row QFN 13x13 This presentation will focus on the package in the center of the board Manufacturing yields and reliability concerns will be specifically discussed 3

4 Problem Description Customer complaining of low manufacturing yields, primarily due to shorts The figure below shows inner pin shorts Other boards showed out pin shorts as well Bridging (shorts) between pins 4

Analysis Initial evaluation on the package itself Package warpage measurements Limited data on Customer board design Cross Sectional analysis performed to determine Extent and location of shorts Via

5 Analysis Initial evaluation on the package itself Package warpage measurements Limited data on Customer board design Cross Sectional analysis performed to determine Extent and location of shorts Via structure and solder escape paths Standoff height MSC Bond-line profile - Top Customer Bond-line profile - Top Outer Inner Thermal Thermal Thermal Inner Outer 0.50 Outer Inner Thermal Thermal Thermal Inner Outer 5

6 Package Analysis TherMoiré tool used to measure warpage across 30 C to 260 C Sample Size; 3 Pre Bake; 125 C Convex/Concave 6

7 Package Analysis Package warpage measurements Package within 50um spec across temperature 7

8 Cross-Sectional Analysis Bridging across outer leads causing shorts Bridging was identified in five locations (fours sets of bridged leads) see red arrows and numbers 8

9 Cross-Sectional Analysis No solder wicking into the Thermal Vias Supposition is that the QFN reached reflow temperature before the PCB Thermal via holes ~19mils (larger then desired) No indication of any via filled material No tenting at bottom or top 9

Cross-Sectional Analysis Bond line thickness measurements Thermal pad standoff ~29um (1.14 mils) Not meeting IPC target of 2.5-3.

10 Cross-Sectional Analysis Bond line thickness measurements Thermal pad standoff ~29um (1.14 mils) Not meeting IPC target of mils Data shows package concave profile Center Cross Sections (Thermal Pad and 2 Leads) Bond-line Thickness Measurements Board ID Part ID Left Lead (Outer) Left Lead (Inner) Thermal Pad Right Lead (Inner) Right Lead (Outer) Manufacturing A Manufacturing A Evaluation U N/A 1.30 N/A

recommend a more traditional pattern as show below Target

11 Stencil Design Evaluation Customer Stencil Design Customer Thermal Pad Design Only allows 34% solder coverage We recommend a more traditional pattern as show below Target solder coverage is 65-85% Minimal 6mil spacing between print areas 11

Stencil Design Evaluation Stencil Comparison The top-left column is

Engineering board with our stencil design The top-right column is

Engineering board with the Customer stencil design This clearly

12 Stencil Design Evaluation Stencil Comparison The top-left column is our stencil design The bottom-left is an over lay of the Engineering board with our stencil design The top-right column is the Customer stencil design The bottom-right is an over lay of the Engineering board with the Customer stencil design This clearly shows the excess solder we have calculated and are seeing on the actual boards 12

13 Stencil Design Evaluation Customer Stencil Overlay Close up Paste is yellow, copper is Red 1.0mm aperture Length 0.70mm Cu Pad Length 36% Coverage 0.50mm aperture Length 0.45mm Cu Pad Length 0.20mm aperture Width 0.22mm aperture Width 0.25mm Cu Pad Width 0.25mm Cu Pad Width 13

14 Stencil Design Evaluation Customer aperture shape oval vs. bullet shape Potential for more solder to Short to adjacent pins NOTE: Oval within the bullet shape 14

Addressing Manufacturing Yields Thermal Pad

78% Coverage No Solder in Thermal Vias No

15 Addressing Manufacturing Yields Thermal Pad X-Rays Shows Concerns regarding Thermal Pad coverage not an issue No Solder in Thermal Vias Customer Stencil 36% Coverage Our Stencil 78% Coverage No Solder in Thermal Vias No Bridging or Voids on either board Solder in Thermal Vias 15

16 Addressing Manufacturing Yields More X-Rays; Titled Axis MSC Stencil MSC Stencil MSC Stencil Customer Stencil Customer Stencil Customer Stencil 16

Addressing Manufacturing Yields Testing Stencil

solder coverage with no bridging across any of the

Testing Stencil Designs Customer Stencil Note extra

17 Addressing Manufacturing Yields Testing Stencil Designs Our Stencil X-Ray images show very clean solder coverage with no bridging across any of the pads Customer Stencil Excess solder (heel) Our Stencil Testing Stencil Designs Customer Stencil Note extra heel of excess solder due to aperture opening too large for copper pad 17

18 Addressing Manufacturing Yields Top View Our stencil Much more copper visible Customer Stencil Our Stencil Top View Customer stencil Much more solder on copper pads 18

cleaning Alternating Inner and Outer Pins MSC Stencil

19 Addressing Manufacturing Yields Top View High Mag. 50x Customer Stencil Solder paste residual after cleaning Alternating Inner and Outer Pins MSC Stencil Very clean solder joint and cu pad Alternating Inner and Outer Pins 19

20 Addressing Manufacturing Yields Edge View Customer Stencil Inner Pins Outer Pins Alternating Inner and Outer Pins MSC Stencil Inner Pins Outer Pins Alternating Inner and Outer Pins 20

21 Addressing Manufacturing Yields Edge View High Mag. 50x Customer Stencil Inner Pins Outer Pins Alternating Inner and Outer Pins MSC Stencil Inner Pins Outer Pins Alternating Inner and Outer Pins 21

22 Addressing Manufacturing Yields Preparing additional Cross Sections Recommend 7 data points per line; Outer, Inner, Thermal (Left, Center, Right,) Inner, Outer 22

23 Addressing Manufacturing Yields Cross Section Customer Standoff Detail Location um Location um Location um Location um Location um Location um Location um Location um Location um Location um Location um Location um Location um Location um Location um Location um Location um Location um Location um Location um Location um 23

Discussion Stencil DOE Assessment The board with 78%

of the 12 vias have some measure of solder in the holes

cross sections indicating that the overall volume of

Note bulbous joints on the I/O pads indicating that the

24 Discussion Stencil DOE Assessment The board with 78% coverage has voiding in a random pattern and shows that 8 of the 12 vias have some measure of solder in the holes MSC There is little push out on the I/O joints in the cross sections indicating that the overall volume of paste there is on target. Note bulbous joints on the I/O pads indicating that the part again was pulled down by the thermal pad and the paste was pushed out on the I/Os MSC Cust MSC CUST 24

25 Discussion Stencil DOE Assessment continued The volume of paste in the vias indicates that this reflow profile brings the PCB to temp just prior to the QFN. This is what I would expect of a reflow profile SMTA journal indicates several benefits to using a crosshatch pattern thermal pad. Helps avoid depositing solder directly over thermal vias Allows excellent escape paths for volatiles 25

26 Improving Reliability Further Studies The next set of evaluations involved gathering IPC9701 data (Performance Test Methods and Qualification Requirements for Surface Mount Solder) Twelve reliability boards were used Three (3) Type-7 plugged vias using MSC stencil Three (3) open vias using MSC stencil Three (3) Type-7 plugged vias using hybrid stencil Three (3) open vias using hybrid stencil Four (4) boards (2 each) subjected to Temp Cycle One each to be cross sectioned; total 4 boards Serialized-Daisy Chain packages with Shodowmorie test will be used 26

27 Improving Reliability Ensure use condition exceeds expected life 27

28 Improving Reliability DfR 4 Open Vias- Middle (Bd 1-U12) Hybrid 25 Open Vias- Middle (Bd 7-U5) % Slope or 0.87 drop % Slope or 0.96 drop Outer Inner Thermal Thermal Thermal Inner Outer Outer Inner Thermal Thermal Thermal Inner Outer DfR 4 Filled Vias- Middle (Bd 2-U7) Hybrid 25 Filled Vias- Middle (Bd 8-U5) % Slope or 1.09 drop % Slope or 1.28 drop Outer Inner Thermal Thermal Thermal Inner Outer 0.50 Outer Inner Thermal Thermal Thermal Inner Outer 28

29 Recommendations PCB The lower number of vias the better Smaller Thermal via drill holes (8-10mil is better than 17-19mils) Smaller outer pads (0.5) and/or cover edge with solder mask Filled vias or place the vias in the streets between the print zones, if possible 29

30 Recommendations Stencil Minimum of 5mil (0.12mm) Laser Cut Stencil with electropolished aperture walls Based on a copper pad 0.25x0.70mm outer and 0.25x0.45mm inner the recommended aperture configuration is 0.25x0.50mm outer and 0.25x0.45mm inner. Use oval shape to get optimum paste release and minimize clogging Use a stainless steel squeegee applied at 45-60ºangle. Squeegee speed must be reduced to fill the aperture during print cycle Thermal pad coverage needs to target 65-85% coverage to achieve stand-off, using a 3x3 array with each opening noted herein 30

31 Conclusion The customer approached Microsemi with a board-level manufacturing yield issue The data supports that adjusting the stencil apertures on the I/O s help address the issues with shorts However, there are many other process variobale that also need to be control The data shows that proper thermal pad stencil design can achieve the desired standoff height to achieve high reliability 31

32 Thank You! Questions? Larry

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