Computer Organization and Architecture, Pt. 1
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1 Computer Organization and Architecture, Pt. Charles Abzug, Ph.D. Department of Computer Science James Madison University Harrisonburg, VA 2287 Voice Phone: , Home Page: 2 Charles Abzug
2 Carpinelli Table.: BASIC BOOLEAN FUNCTIONS I Original figure or table 2 by Addison Wesley Longman, Inc 24-Feb Charles Abzug 2
3 Carpinelli Table.2: BASIC BOOLEAN FUNCTIONS II Original figure or table 2 by Addison Wesley Longman, Inc 24-Feb Charles Abzug 3
4 Notation for Boolean Logical Operations A Ā ~A!A NOT A X Y X+Y X OR Y X Y X Y XY X AND Y X NAND Y X NOR Y X Y X XOR Y X XNOR Y 24-Feb Charles Abzug 4
5 Carpinelli Table.3: ALL POSSIBLE BOOLEAN FUNCTIONS of TWO INPUT VARIABLES x y x y x y Original figure or table 2 by Addison Wesley Longman, Inc 24-Feb Charles Abzug 5
6 Carpinelli Table.4: TRUTH TABLE for a COMPOSITE BOOLEAN FUNCTION F(x,y) = x y + y z Original figure or table 2 by Addison Wesley Longman, Inc 24-Feb Charles Abzug 6
7 Carpinelli Table.5: TRUTH TABLE for another COMPOSITE BOOLEAN FUNCTION F(x,y) = (x + y ) (y + z) Original figure or table 2 by Addison Wesley Longman, Inc 24-Feb Charles Abzug 7
8 Carpinelli Table.6: TRUTH TABLES DEMONSTRATING ALGEBRAIC EQUIVALENCES RESULTING from DeMORGAN S THEOREMS F(x,y) = (x y + y z) = (x + y) (y + z) = x y + x z + y z Original figure or table 2 by Addison Wesley Longman, Inc 24-Feb Charles Abzug 8
9 Carpinelli Figure.: BASIC KARNAUGH MAPS (3-variable and 4-variable) Original figure or table 2 by Addison Wesley Longman, Inc 24-Feb Charles Abzug 9
10 Carpinelli Figure.2: GENERATION of GRAY CODE Original figure or table 2 by Addison Wesley Longman, Inc 24-Feb Charles Abzug
11 Carpinelli Figure.3: SAMPLE 3-VARIABLE KARNAUGH MAP SHOWING ALGEBRAIC SIMPLIFICATION Original figure or table 2 by Addison Wesley Longman, Inc 24-Feb Charles Abzug
12 Carpinelli Figure.4: SAMPLE 4-VARIABLE KARNAUGH MAP SHOWING ALGEBRAIC SIMPLIFICATION Original figure or table 2 by Addison Wesley Longman, Inc 24-Feb Charles Abzug 2
13 Carpinelli Figure.5 : ANOTHER 4-VARIABLE KARNAUGH MAP SHOWING ALGEBRAIC SIMPLIFICATION Original figure or table 2 by Addison Wesley Longman, Inc 24-Feb Charles Abzug 3
14 Carpinelli Figure.7: LOGIC CIRCUITS IMPLEMENTING a BOOLEAN FUNCTION Original figure or table 2 by Addison Wesley Longman, Inc 24-Feb Charles Abzug 4
15 Carpinelli Figure.7: LOGIC CIRCUITS IMPLEMENTING a BOOLEAN FUNCTION NOTE: This is a three-stage circuit first stage AND gates, second stage one OR and one AND gate, third stage an OR gate. This is not how we implement a Boolean function normally. Original figure or table 2 by Addison Wesley Longman, Inc This is a normal logic-circuit implementation of a Boolean function. 24-Feb Charles Abzug 5
16 Carpinelli Figure.8: SIMPLE BUFFER GATE and TRI-STATE GATES Original figure or table 2 by Addison Wesley Longman, Inc 24-Feb Charles Abzug 6
17 Carpinelli Table.7, as it appears in the text: TRUTH TABLES for BUFFER GATES Simple Buffer Tri-State Buffer Tri-State Buffer Gate (Active-High Enable) (Active-Low Enable) Original figure or table 2 by Addison Wesley Longman, Inc 24-Feb Charles Abzug 7
18 Carpinelli Table.7, TRUTH TABLES FOR BUFFER GATES CORRECTED to COUNTING ORDER: Simple Buffer Tri-State Buffer Tri-State Buffer Gate (Active-High Enable) (Active-Low Enable) Original figure or table 2 by Addison Wesley Longman, Inc Truth Tables in Counting Order: E In X Out Z E In Out X Z 24-Feb Charles Abzug 8
19 BCD-to-Seven-Segment Decoder: SEGMENT LABELS a f b g e c d 24-Feb Charles Abzug 9
20 Carpinelli Figure.22: BCD-to-SEVEN-SEGMENT DECODERS: TRUTH TABLES for all SEVEN BOOLEAN FUNCTIONS Original figure or table 2 by Addison Wesley Longman, Inc 24-Feb Charles Abzug 2
21 Carpinelli Figure.23 (a): KARNAUGH MAP SIMPLIFICATION of TWO BOOLEAN FUNCTIONS Original figure or table 2 by Addison Wesley Longman, Inc 24-Feb Charles Abzug 2
22 Carpinelli Figure.23 (b): LOGICAL CIRCUITS IMPLEMENTING TWO BOOLEAN FUNCTIONS Original figure or table 2 by Addison Wesley Longman, Inc 24-Feb Charles Abzug 22
23 Carpinelli Figure.9 (a): MULTIPLEXOR Original figure or table 2 by Addison Wesley Longman, Inc 24-Feb Charles Abzug 23
24 Carpinelli Figure.9 (b), as it appears in the text: Original figure or table 2 by Addison Wesley Longman, Inc 24-Feb Charles Abzug 24
25 Carpinelli Figure.9 (b), CORRECTED: Original figure or table 2 by Addison Wesley Longman, Inc E S S Out X X Z Truth Table is now in Counting Order: Input Input Input 2 Input 3 24-Feb Charles Abzug 25
26 Carpinelli Figure.9 (c), as it appears in the text: Original figure or table 2 by Addison Wesley Longman, Inc 24-Feb Charles Abzug 26
27 Carpinelli Figure.9 (c), CORRECTED: Original figure or table 2 by Addison Wesley Longman, Inc E S S Out Input Truth Table is now in Counting Order: Input Input 2 Input 3 X X Z 24-Feb Charles Abzug 27
28 Carpinelli Figure.: CONSTRUCTION of a 4- MULTIPLEXOR from THREE 2- MULTIPLEXORS Original figure or table 2 by Addison Wesley Longman, Inc 24-Feb Charles Abzug 28
29 Carpinelli Figure. (a), as it appears in the text: DECODER Original figure or table 2 by Addison Wesley Longman, Inc 24-Feb Charles Abzug 29
30 Carpinelli Figure. (a), showing CORRECTION: Remove this dot. Original figure or table 2 by Addison Wesley Longman, Inc 24-Feb Charles Abzug 3
31 Carpinelli Figure. (b), as it appears in the text: Original figure or table 2 by Addison Wesley Longman, Inc 24-Feb Charles Abzug 3
32 Carpinelli Figure. (b), CORRRECTED: Original figure or table 2 by Addison Wesley Longman, Inc E S S Out Out Out 2 Out 3 Truth Table with several corrections, and in Counting Order: X X Z Z Z Z 24-Feb Charles Abzug 32
33 Carpinelli Figure. (c), as it appears in the text: Original figure or table 2 by Addison Wesley Longman, Inc 24-Feb Charles Abzug 33
34 Carpinelli Figure. (c), CORRECTED: Original figure or table 2 by Addison Wesley Longman, Inc E S S Out Out Out 2 Out 3 Truth Table with several corrections, and in Counting Order: X X Z Z Z Z 24-Feb Charles Abzug 34
35 Carpinelli Figure.2 (a): SIMPLE ENCODER Original figure or table 2 by Addison Wesley Longman, Inc 24-Feb Charles Abzug 35
36 Carpinelli Figure.2 (b), as it appears in the text: Original figure or table 2 by Addison Wesley Longman, Inc 24-Feb Charles Abzug 36
37 Carpinelli Figure.2 (b), CORRECTED: Original figure or table 2 by Addison Wesley Longman, Inc E I 3 I 2 I I S S V Abbreviated Truth Table in Counting Order (not all input combinations are shown, since external constraints allow at most one input line to have a value of ): X X X X Z Z Z 24-Feb Charles Abzug 37
38 Carpinelli Figure.2 (c), as it appears in the text: Original figure or table 2 by Addison Wesley Longman, Inc 24-Feb Charles Abzug 38
39 Carpinelli Figure.2 (c), CORRECTED: Original figure or table 2 by Addison Wesley Longman, Inc Abbreviated Truth Table in Counting Order (not all input combinations are shown, since external constraints allow at most one input line to have a value of ): E I 3 X I 2 X I X I X S Z S Z V Z 24-Feb Charles Abzug 39
40 Carpinelli Figure.3 (a): PRIORITY ENCODER Original figure or table 2 by Addison Wesley Longman, Inc 24-Feb Charles Abzug 4
41 Carpinelli Figure.3 (b) and (c) PRIORITY ENCODER (alternative version) Original figure or table 2 by Addison Wesley Longman, Inc 24-Feb Charles Abzug 4
42 Carpinelli Figure.4: ONE-BIT COMPARATOR Original figure or table 2 by Addison Wesley Longman, Inc 24-Feb Charles Abzug 42
43 Carpinelli Figure.5, as it appears in the text: SINGLE-BIT STAGE of a MULTI-BIT COMPARATOR Original figure or table 2 by Addison Wesley Longman, Inc 24-Feb Charles Abzug 43
44 Carpinelli Figure.5, CORRECTED: SINGLE-BIT STAGE of a MULTI-BIT COMPARATOR ( ) ( ) ( ) ( ) ( ) ( ) Original figure or table 2 by Addison Wesley Longman, Inc 24-Feb Charles Abzug 44
45 Carpinelli Figure.6, as it appears in the text: Original figure or table 2 by Addison Wesley Longman, Inc 24-Feb Charles Abzug 45
46 Carpinelli Figure.6, CORRECTED: ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) Original figure or table 2 by Addison Wesley Longman, Inc 24-Feb Charles Abzug 46
47 Carpinelli Figure.7: HALF ADDER Original figure or table 2 by Addison Wesley Longman, Inc 24-Feb Charles Abzug 47
48 Carpinelli Figure.8, as it appears in the text: FULL ADDER Original figure or table 2 by Addison Wesley Longman, Inc 24-Feb Charles Abzug 48
49 Carpinelli Figure.8, CORRECTED: FULL ADDER Original figure or table 2 by Addison Wesley Longman, Inc 24-Feb Charles Abzug 49
50 Carpinelli Figure.9, as it appears in the text: FOUR-BIT ADDER Original figure or table 2 by Addison Wesley Longman, Inc 24-Feb Charles Abzug 5
51 Carpinelli Figure.9, CORRECTED: FOUR-BIT ADDER X C Original figure or table 2 by Addison Wesley Longman, Inc 24-Feb Charles Abzug 5
52 Carpinelli Figure.2: SUBTRACTOR Original figure or table 2 by Addison Wesley Longman, Inc 24-Feb Charles Abzug 52
53 Carpinelli Figure.2, as it appears in the text: MEMORY MODULES Original figure or table 2 by Addison Wesley Longman, Inc 24-Feb Charles Abzug 53
54 Carpinelli Figure.2, ENHANCED: MEMORY MODULES ROM RAM Original figure or table 2 by Addison Wesley Longman, Inc 24-Feb Charles Abzug 54
55 USE of MULTIPLE MEMORY MODULES. In general, a MEMORY consists of some number of addressable units, each of which is called a WORD. 2. The contents of a single word of memory are described as a string of bits. The words in a computer memory are all of identical width, w, and can be described as : D (w-) D (w-2) D (w-3)... D. 3. For a memory containing a total of T words, it is necessary to specify a numeric address in order to be able to uniquely identify each word. For this purpose, some number of address bits is necessary. The required number of address bits is given by: A > log 2 (T) 4. We can construct the memory from a number of memory modules of equal size. If each module contains N words, then the individual module requires n address bits to specify which word within the module is to be accessed. Since N is always an exact power of 2, n = log 2 (N) 24-Feb Charles Abzug 55
56 USE of MULTIPLE MEMORY MODULES (continued) 5. For a total of T words, the number of modules (memory chips) required is: M = T /N log 2 (M) = log 2 (T) - log 2 N 6. The total address lines are thus divided into two groups: m chip-select lines, and n within-chip word-select lines: A = m + n 7. The n within-chip address lines are connected in parallel to the addressselect input terminals of all of the memory modules. 8. The m chip-select lines go to an (m-x-2 m ) decoder. Each output line from the decoder connects to the Chip-Enable input line of one memory chip. 24-Feb Charles Abzug 56
57 Carpinelli Figure.24 (a), as it appears in the text: TWO-NUMBER SORTER Original figure or table 2 by Addison Wesley Longman, Inc 24-Feb Charles Abzug 57
58 Carpinelli Figure.24 (a), CORRECTED: TWO-NUMBER SORTER Comparator Original figure or table 2 by Addison Wesley Longman, Inc 24-Feb Charles Abzug 58
59 Carpinelli Figure.24 (b): FOUR-NUMBER SORTER Original figure or table 2 by Addison Wesley Longman, Inc 24-Feb Charles Abzug 59
60 TWO PRINCIPAL TYPES of LOGIC CIRCUITS:. COMBINATIONAL 2. SEQUENTIAL 24-Feb Charles Abzug 6
61 TWO PRINCIPAL TYPES of LOGIC CIRCUITS:. COMBINATIONAL Current output (s and s), after the passage of sufficient time to allow for circuit stabilization, is dependent solely upon current input (s and s), 2. SEQUENTIAL Current output depends not only on current input, but also on the prior history of the circuit state. 24-Feb Charles Abzug 6
62 Carpinelli Figure.25 Original figure or table 2 by Addison Wesley Longman, Inc 24-Feb Charles Abzug 62
63 Carpinelli Figure.26 (a): POSITIVE-EDGE-TRIGGERED D FLIP-FLOP Original figure or table 2 by Addison Wesley Longman, Inc 24-Feb Charles Abzug 63
64 Carpinelli Figure.26 (b): POSITIVE-GATED D LATCH Original figure or table 2 by Addison Wesley Longman, Inc 24-Feb Charles Abzug 64
65 Carpinelli Figure.27: POSITIVE-GATED D LATCH, with Asynchronous SET and CLEAR Original figure or table 2 by Addison Wesley Longman, Inc 24-Feb Charles Abzug 65
66 Carpinelli Figure.28: SR LATCH Original figure or table 2 by Addison Wesley Longman, Inc 24-Feb Charles Abzug 66
67 Carpinelli Figure.25: POSITIVE-EDGE-TRIGGERED JK FLIP-FLOP Original figure or table 2 by Addison Wesley Longman, Inc 24-Feb Charles Abzug 67
68 Carpinelli Figure.3: POSITIVE-EDGE-TRIGGERED T FLIP-FLOP Original figure or table 2 by Addison Wesley Longman, Inc 24-Feb Charles Abzug 68
69 Carpinelli Figure.3, as it appears in the text: FOUR-BIT REGISTER (not a 4-Bit Flip-Flop) Original figure or table 2 by Addison Wesley Longman, Inc 24-Feb Charles Abzug 69
70 Carpinelli Figure.3, CORRECTED: FOUR-BIT REGISTER (not a 4-Bit Flip-Flop) XD XD XD XD XD Original figure or table 2 by Addison Wesley Longman, Inc 24-Feb Charles Abzug 7
71 Carpinelli Figure.32, as it appears in the text: Four-Bit Incrementing ( Up ) Counter Original figure or table 2 by Addison Wesley Longman, Inc 24-Feb Charles Abzug 7
72 Carpinelli Figure.32, CORRECTED: Four-Bit Incrementing ( Up ) Counter DX DX DX DX Original figure or table 2 by Addison Wesley Longman, Inc 24-Feb Charles Abzug 72
73 Carpinelli Figure.33: FOUR-BIT INCREMENTING/DECREMENTING COUNTER ( Up/Down Counter) Original figure or table 2 by Addison Wesley Longman, Inc 24-Feb Charles Abzug 73
74 Carpinelli Figure.34: FOUR-BIT LEFT-SHIFT REGISTER Original figure or table 2 by Addison Wesley Longman, Inc 24-Feb Charles Abzug 74
75 Carpinelli Table.8, as it appears in the text: SHIFT OPERATIONS Original figure or table 2 by Addison Wesley Longman, Inc 24-Feb Charles Abzug 75
76 Carpinelli Table.8, CORRECTED: SHIFT OPERATIONS The corrected version corresponds to the definitions of the various types of shift operations typically implemented in the Arithmetic Logic Unit (ALU) portion of Central Processing Units (CPUs). Logical XXXXXX Logical XXXXXX HHHHHHH X 2 X X HHHHHHH X 3 X 2 X HHHHHHH X 2 X X Original figure or table 2 by Addison Wesley Longman, Inc 24-Feb Charles Abzug 76
77 Carpinelli Figure.35: PROGRAMMABLE LOGIC ARRAY (PLA) Original figure or table 2 by Addison Wesley Longman, Inc 24-Feb Charles Abzug 77
78 Carpinelli Figure.36: PROGRAMMABLE ARRAY of LOGIC (PAL) Original figure or table 2 by Addison Wesley Longman, Inc 24-Feb Charles Abzug 78
79 Carpinelli Problem.9: F = WXY + WXZ + W XY + XYZ = (WXY Z + WXY Z ) + (WXYZ + WXY Z) + (W XYZ + W XYZ ) + (WXYZ + W XYZ ) Original figure or table 2 by Addison Wesley Longman, Inc 24-Feb Charles Abzug 79
80 CARRY-LOOKAHEAD ADDER g i = X i Y i p i = X i + Y i (not X i Y i ) 24-Feb Charles Abzug 8
81 FINITE-STATE MACHINES: SEQUENTIAL and COMBINATIONAL LOGIC 24-Feb Charles Abzug 8
82 Carpinelli Figure 2. (a): GENERIC STATE-MACHINE MODEL Original figure or table 2 by Addison Wesley Longman, Inc 24-Feb Charles Abzug 82
83 Carpinelli Figure 2.3: STATE DIAGRAMS for the JK FLIP-FLOP Original figure or table 2 by Addison Wesley Longman, Inc 24-Feb Charles Abzug 83
84 Carpinelli Figure 2.4: JK FLIP-FLOP State Table: State Diagram: Original figure or table 2 by Addison Wesley Longman, Inc 24-Feb Charles Abzug 84
85 Carpinelli Figure 2.5 (b): STATE DIAGRAM for the MODULO-6 COUNTER: MOORE MACHINE Original figure or table 2 by Addison Wesley Longman, Inc 24-Feb Charles Abzug 85
86 Carpinelli Figure 2.6 (b): STATE DIAGRAM for the STRING-CHECKER: MOORE MACHINE Original figure or table 2 by Addison Wesley Longman, Inc 24-Feb Charles Abzug 86
87 Carpinelli Figure 2.A (b): STATE DIAGRAM for the STRING-CHECKER with REVISED STATE ASSIGNMENTS: MOORE MACHINE Original figure or table 2 by Addison Wesley Longman, Inc 24-Feb Charles Abzug 87
88 Carpinelli Figure 2.7, as it appears in the text: STATE DIAGRAM for the TOLL-BOOTH CONTROLLER: MOORE MACHINE Original figure or table 2 by Addison Wesley Longman, Inc 24-Feb Charles Abzug 88
89 Carpinelli Figure 2.7, CORRECTED: STATE DIAGRAM for the TOLL-BOOTH CONTROLLER: MOORE MACHINE Original figure or table 2 by Addison Wesley Longman, Inc I I I I XX XX 24-Feb Charles Abzug 89
90 Carpinelli Table 2.5: STATES for the TOLL-BOOTH CONTROLLER: MOORE MACHINE Original figure or table 2 by Addison Wesley Longman, Inc 24-Feb Charles Abzug 9
91 Carpinelli Table 2.6: STATE TABLE for the TOOL-BOOTH CONTROLLER: MOORE MACHINE Original figure or table 2 by Addison Wesley Longman, Inc 24-Feb Charles Abzug 9
92 Carpinelli Figure 2.8 (b): STATE DIAGRAM for the MODULO-6 COUNTER: MOORE MACHINE (Assigned State Values Included Original figure or table 2 by Addison Wesley Longman, Inc 24-Feb Charles Abzug 92
93 Carpinelli Figure 2. (a): GENERIC MOORE MACHINE Original figure or table 2 by Addison Wesley Longman, Inc 24-Feb Charles Abzug 93
94 Carpinelli Figure 2. (b): MOORE MACHINE IMPLEMENTATION of the MODULO-6 COUNTER Original figure or table 2 by Addison Wesley Longman, Inc 24-Feb Charles Abzug 94
95 Carpinelli Figure 2.: KARNAUGH MAPS for the NEXT STATE of the MODULO-6 COUNTER Original figure or table 2 by Addison Wesley Longman, Inc 24-Feb Charles Abzug 95
96 END 24-Feb Charles Abzug 96
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